The fabrication of integrated chips can be broadly separated into two main sections, front-end-of-the-line (FEOL) fabrication and back-end-of-the-line (BEOL) fabrication. FEOL fabrication includes the formation of devices (e.g., transistors, capacitors, resistors, etc.) within a semiconductor substrate. BEOL fabrication includes the formation of one or more metal interconnect layers comprised within one or more insulating dielectric layers disposed above the semiconductor substrate. The metal interconnect layers of the BEOL electrically connect individual devices of the FEOL to external pins of an integrated chip.
As the size of a semiconductor device size decreases, the capacitive coupling between the metal interconnect layers of the BEOL tends to increase since the capacitive coupling is inversely proportional to the distance between the metal interconnect layers. This coupling may ultimately limit the speed of the chip or otherwise inhibit proper chip operation if steps are not taken to reduce the capacitive coupling. Accordingly, a need has developed in the art for an improved method of forming an interconnect structure for an integrated chip.